Semiconductor device

ABSTRACT

A semiconductor device includes a fin-shaped silicon layer on a silicon substrate surface. The fin-shaped silicon layer has a longitudinal axis extending in a first direction parallel to the surface and a first insulating film is around the fin-shaped silicon layer. A pillar-shaped silicon layer is on the fin-shaped silicon layer, and a pillar diameter of the bottom of the pillar-shaped silicon layer is equal to a fin width of the top of the fin-shaped silicon layer. The pillar diameter and the fin width are parallel to the surface. A gate insulating film is around the pillar-shaped silicon layer and a metal gate electrode is around the gate insulating film. A metal gate wiring is connected to the metal gate electrode and has a longitudinal axis extending in a second direction parallel to the surface and perpendicular to the first direction of the longitudinal axis of the fin-shaped silicon layer.

RELATED APPLICATIONS

This application is continuation of U.S. patent application Ser. No. 14/061,082 filed Oct. 23, 2013, which is a divisional application of U.S. patent application Ser. No. 13/666,445 filed on Nov. 1, 2012, now U.S. Pat. No. 8,759,178, which, pursuant to 35 U.S.C. §119(e), claims the benefit of U.S. Provisional Application No. 61/557,501 filed on Nov. 9, 2011. The entire disclosures of which are incorporated by reference herein.

BACKGROUND

1. Technical Field

The present invention relates to a semiconductor device.

2. Description of the Related Art

Semiconductor integrated circuits, particularly integrated circuits using MOS transistors, are increasing in integration. With increases in integration, MOS transistors used in the integrated circuits are increasingly made finer up to a nano region. Finer MOS transistors have the problem of difficulty in suppressing leak currents and difficulty in decreasing the areas occupied by circuits because of the demand for securing necessary amounts of currents. In order to resolve the problem, there have been proposed surrounding gate transistors (SGT) having a structure in which a source, a gate, and a drain are disposed in a direction vertical to a substrate, and the gate surrounds a pillar-shaped semiconductor layer (for example, Japanese Unexamined Patent Application Publication Nos. 2-71556, 2-188966, and 3-145761).

By using a metal for a gate electrode instead of using polysilicon, depletion can be suppressed, and the resistance of the gate electrode can be decreased. However, a manufacturing process after a metal gate is formed must be one in which metal contamination by the metal gate is always taken into consideration.

In addition, in order to satisfy both a metal gate process and a high-temperature process for usual MOS transistors, a metal gate last process is used for actual products, in which a metal gate is formed after a high-temperature process (IEDM 2007 K. Mistry, et. al., pp. 247-250). The gate is formed using polysilicon, and then an interlayer insulating film is deposited. Then, the polysilicon gate is exposed by chemical mechanical polishing and etched, followed by deposition of a metal. Therefore, in order to satisfy both the metal gate process and the high-temperature process, the metal gate last process must be used for SGT, in which a metal gate is formed after the high-temperature process. Since, in the SGT, the upper surface of the pillar-shaped silicon layer is higher than the gate, some consideration is required for using the metal gate last process.

In addition, usual MOS transistors use a first insulating film in order to decrease a parasitic capacitance between gate wiring and a substrate. For example, in FINFET (IEDM 2010 CC. Wu, et. al., 27.1.1-27.1.4.), a first insulating film is formed around a fin-shaped semiconductor layer and then etched back to expose the fin-shaped semiconductor layer, thereby decreasing the parasitic capacitance between the gate wiring and the substrate. Also, in SGT, the first insulating film must be used for decreasing the parasitic capacitance between the gate wiring and the substrate. The SGT includes the pillar-shaped semiconductor layer in addition to the fin-shaped semiconductor layer, and thus some consideration is required for forming the pillar-shaped semiconductor layer.

SUMMARY

Accordingly, an object is to decrease a parasitic capacitance between a gate wiring and a substrate, provide a SGT manufacturing method using a gate last process, and provide a resulting SGT structure.

In one embodiment a semiconductor device includes a fin-shaped silicon layer on a surface of a silicon substrate, the fin-shaped silicon layer having a longitudinal axis extending in a first direction parallel to the surface;

a first insulating film around the fin-shaped silicon layer;

a pillar-shaped silicon layer on the fin-shaped silicon layer, a pillar diameter of the bottom of the pillar-shaped silicon layer being equal to a fin width of the top of the fin-shaped silicon layer, the pillar diameter and the fin width parallel to the surface of the silicon substrate;

a gate insulating film around the pillar-shaped silicon layer;

a metal gate electrode around the gate insulating film; and

a metal gate wiring connected to the metal gate electrode, the metal gate wiring having a longitudinal axis extending in a second direction parallel to the surface and perpendicular to the first direction of the longitudinal axis of the fin-shaped silicon layer.

A method for manufacturing a semiconductor device of the present invention includes:

a first step of forming a fin-shaped silicon layer on a silicon substrate, forming a first insulating film around the fin-shaped silicon layer, and forming a pillar-shaped silicon layer on the fin-shaped silicon layer, the width of the pillar-shaped silicon layer being equal to the width of the fin-shaped silicon layer;

a second step of, after the first step, forming diffusion layers by implanting impurities in an upper portion of the pillar-shaped silicon layer, an upper portion of the fin-shaped silicon layer, and a lower portion of the pillar-shaped silicon layer;

a third step of, after the second step, forming a gate insulating film, a polysilicon gate electrode, and a polysilicon gate wiring so that the gate insulating film covers the periphery and the top of the pillar-shaped silicon layer, the polysilicon gate electrode covers the gate insulating film, and after the polysilicon gate electrode and the polysilicon gate wiring are formed, the upper surface of polysilicon is higher than the gate insulating film on the diffusion layer formed in the upper portion of the pillar-shaped silicon layer;

a fourth step of, after the third step, forming a silicide in an upper portion of the diffusion layer in the upper portion of the fin-shaped silicon layer;

a fifth step of, after the fourth step, depositing an interlayer insulating film, exposing the polysilicon gate electrode and the polysilicon gate wiring, etching the polysilicon gate electrode and the polysilicon gate wiring, and then depositing a metal to form a metal gate electrode and a metal gate wiring, the metal gate wiring being connected to the metal gate electrode and extending in a direction perpendicular to the fin-shaped silicon layer; and

a sixth step of, after the fifth step, forming a contact so as to make direct contact between the contact and the diffusion layer in the upper portion of the pillar-shaped silicon layer.

The manufacturing method is also characterized in that a first resist is formed for forming the fin-shaped silicon layer on the silicon substrate; the silicon substrate is etched to form the fin-shaped silicon layer and the first resist is removed; the first insulating film is deposited around the fin-shaped silicon layer and then etched back to expose an upper portion of the fin-shaped silicon layer; a second resist is formed to be perpendicular to the fin-shaped silicon layer; the fin-shaped silicon layer is etched; and then the second resist is removed to form the pillar-shaped silicon layer so that a portion where the fin-shaped silicon layer and the second resist intersect at right angles becomes the pillar-shaped silicon layer.

The manufacturing method is further characterized in that in a structure including the fin-shaped silicon layer formed on the silicon substrate, the first insulating film formed around the fin-shaped silicon layer, and the pillar-shaped silicon layer formed on the fin-shaped silicon layer, a second oxide film is deposited, a first nitride film is formed on the second oxide film, the first nitride film is etched to be left as a side wall, the diffusion layers are formed by impurity implantation in an upper portion of the pillar-shaped silicon layer and an upper portion of the fin-shaped silicon layer, and the first nitride film and the second oxide film are removed, followed by heat treatment.

The manufacturing method is further characterized in that in a structure including the fin-shaped silicon layer formed on the silicon substrate, the first insulating film formed around the fin-shaped silicon layer, the pillar-shaped silicon layer formed on the fin-shaped silicon layer, the diffusion layer formed in the upper portion of the fin-shaped silicon layer and in the lower portion of the pillar-shaped silicon layer, and the diffusion layer formed in the upper portion of the pillar-shaped silicon layer, the gate insulating film is formed, polysilicon is deposited and then planarized so that after planarization, the upper surface of the polysilicon is higher than the gate insulating film on the diffusion layer formed in the upper portion of the pillar-shaped silicon layer, a second nitride film is deposited, a third resist is formed for forming the polysilicon gate electrode and the polysilicon gate wiring, the second nitride film is etched, the polysilicon is etched to form the polysilicon gate electrode and the polysilicon gate wiring, the gate insulating film is etched, and the third resist is removed.

The manufacturing method is further characterized in that a third nitride film is deposited and then etched to be left as a side wall, and a metal is deposited to form a silicide in an upper portion of the diffusion layer in the upper portion of the fin-shaped silicon layer.

The manufacturing method is further characterized in that a fourth nitride film is deposited, the interlayer insulating film is deposited and then planarized, the polysilicon gate electrode and the polysilicon gate wiring are exposed, the polysilicon gate electrode and the polysilicon gate wiring are removed, a metal is filled in a portion from which the polysilicon gate electrode and the polysilicon gate wiring have been removed, and the metal is etched to expose the gate insulating film on the diffusion layer in the upper portion of the pillar-shaped silicon layer, thereby forming the metal gate electrode and the metal gate wiring.

A semiconductor device of the present invention includes: a fin-shaped silicon layer formed on a silicon substrate; a first insulating film formed around the fin-shaped silicon layer; a pillar-shaped silicon layer formed on the fin-shaped silicon layer, the width of the pillar-shaped silicon layer being equal to the width of the fin-shaped silicon layer; a diffusion layer formed in an upper portion of the fin-shaped silicon layer and a lower portion of the pillar-shaped silicon layer; a diffusion layer formed in an upper portion of the pillar-shaped silicon layer; a silicide formed in an upper portion of the diffusion layer in the upper portion of the fin-shaped silicon layer; a gate insulating film formed around the pillar-shaped silicon layer; a metal gate electrode formed around the gate insulating film: a metal gate wiring connected to the metal gate electrode and extending in a direction perpendicular to the fin-shaped silicon layer; and a contact formed on the diffusion layer formed in the upper portion of the pillar-shaped silicon layer so as to make direct contact between the contact and the diffusion layer formed in the upper portion of the pillar-shaped silicon layer.

According to the present invention, it is possible to decrease a parasitic capacitance between a gate wiring and a substrate, provide a SGT manufacturing method using a gate last process, and provide a resulting SGT structure.

The fin-shaped silicon layer, the first insulating film, and the pillar-shaped silicon layer are formed based on a conventional FINFET manufacturing method and thus can be easily formed.

In addition, a silicide is generally formed in an upper portion of the pillar-shaped silicon layer, but the silicide must be formed after a polysilicon gate is formed because the deposition temperature of polysilicon is higher than the silicide formation temperature.

Therefore, when the silicide is formed in an upper portion of a silicon column, a hole is formed on a polysilicon gate electrode after the polysilicon gate is formed, the silicide is formed after a side wall composed of an insulating film is formed on the side wall of the hole, and then the hole is filled with an insulating film, thereby causing the problem of increasing the number of manufacturing steps. Therefore, the diffusion layers are formed before the polysilicon gate electrode and the polysilicon gate wiring are formed, the pillar-shaped silicon layer is covered with the polysilicon gate electrode, and the silicide is formed only in an upper portion of the fin-shaped silicon layer. Therefore, a usual metal gate last manufacturing method can be used, in which a gate is formed using polysilicon, the interlayer insulating film is deposited, the polysilicon gate is exposed by chemical mechanical polishing and then etched, and then a metal is deposited, thereby facilitating the formation of metal gate SGT.

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1A is a plan view of a semiconductor device according to the present invention, FIG. 1B is a sectional view taken along line X-X′ in FIG. 1A, and FIG. 1C is a sectional view taken along line Y-Y′ in FIG. 1A.

FIG. 2A is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 2B is a sectional view taken along line X-X′ in FIG. 2A, and FIG. 2C is a sectional view taken along line Y-Y′ in FIG. 2A.

FIG. 3A is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 3B is a sectional view taken along line X-X′ in FIG. 3A, and FIG. 3C is a sectional view taken along line Y-Y′ in FIG. 3A.

FIG. 4A is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 4B is a sectional view taken along line X-X′ in FIG. 4A, and FIG. 4C is a sectional view taken along line Y-Y′ in FIG. 4A.

FIG. 5A is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 5B is a sectional view taken along line X-X′ in FIG. 5A, and FIG. 5C is a sectional view taken along line Y-Y′ in FIG. 5A.

FIG. 6A is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 6B is a sectional view taken along line X-X′ in FIG. 6A, and FIG. 6C is a sectional view taken along line Y-Y′ in FIG. 6A.

FIG. 7A is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 7B is a sectional view taken along line X-X′ in FIG. 7A, and FIG. 7C is a sectional view taken along line Y-Y′ in FIG. 7A.

FIG. 8A is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 8B is a sectional view taken along line X-X′ in FIG. 8A, and FIG. 8C is a sectional view taken along line Y-Y′ in FIG. 8A.

FIG. 9A is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 9B is a sectional view taken along line X-X′ in FIG. 9A, and FIG. 9C is a sectional view taken along line Y-Y′ in FIG. 9A.

FIG. 10A is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 10B is a sectional view taken along line X-X′ in FIG. 10A, and FIG. 10C is a sectional view taken along line Y-Y′ in FIG. 10A.

FIG. 11A is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 11B is a sectional view taken along line X-X′ in FIG. 11A, and FIG. 11C is a sectional view taken along line Y-Y′ in FIG. 11A.

FIG. 12A is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 12B is a sectional view taken along line X-X′ in FIG. 12A, and FIG. 12C is a sectional view taken along line Y-Y′ in FIG. 12A.

FIG. 13A is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 13B is a sectional view taken along line X-X′ in FIG. 13A, and FIG. 13C is a sectional view taken along line Y-Y′ in FIG. 13A.

FIG. 14A is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 14B is a sectional view taken along line X-X′ in FIG. 14A, and FIG. 14C is a sectional view taken along line Y-Y′ in FIG. 14A.

FIG. 15A is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 15B is a sectional view taken along line X-X′ in FIG. 15A, and FIG. 15C is a sectional view taken along line Y-Y′ in FIG. 15A.

FIG. 16A is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 16B is a sectional view taken along line X-X′ in FIG. 16A, and FIG. 16C is a sectional view taken along line Y-Y′ in FIG. 16A.

FIG. 17A is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 17B is a sectional view taken along line X-X′ in FIG. 17A, and FIG. 17C is a sectional view taken along line Y-Y′ in FIG. 17A.

FIG. 18A is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 18B is a sectional view taken along line X-X′ in FIG. 18A, and FIG. 18C is a sectional view taken along line Y-Y′ in FIG. 18A.

FIG. 19A is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 19B is a sectional view taken along line X-X′ in FIG. 19A, and FIG. 19C is a sectional view taken along line Y-Y′ in FIG. 19A.

FIG. 20A is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 20B is a sectional view taken along line X-X′ in FIG. 20A, and FIG. 20C is a sectional view taken along line Y-Y′ in FIG. 20A.

FIG. 21A is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 21B is a sectional view taken along line X-X′ in FIG. 21A, and FIG. 21C is a sectional view taken along line Y-Y′ in FIG. 21A.

FIG. 22A is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 22B is a sectional view taken along line X-X′ in FIG. 22A, and FIG. 22C is a sectional view taken along line Y-Y′ in FIG. 22A.

FIG. 23A is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 23B is a sectional view taken along line X-X′ in FIG. 23A, and FIG. 23C is a sectional view taken along line Y-Y′ in FIG. 23A.

FIG. 24A is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 24B is a sectional view taken along line X-X′ in FIG. 24A, and FIG. 24C is a sectional view taken along line Y-Y′ in FIG. 24A.

FIG. 25A is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 25B is a sectional view taken along line X-X′ in FIG. 25A, and FIG. 25C is a sectional view taken along line Y-Y′ in FIG. 25A.

FIG. 26A is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 26B is a sectional view taken along line X-X′ in FIG. 26A, and FIG. 26C is a sectional view taken along line Y-Y′ in FIG. 26A.

FIG. 27A is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 27B is a sectional view taken along line X-X′ in FIG. 27A, and FIG. 27C is a sectional view taken along line Y-Y′ in FIG. 27A.

FIG. 28A is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 28B is a sectional view taken along line X-X′ in FIG. 28A, and FIG. 28C is a sectional view taken along line Y-Y′ in FIG. 28A.

FIG. 29A is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 29B is a sectional view taken along line X-X′ in FIG. 29A, and FIG. 29C is a sectional view taken along line Y-Y′ in FIG. 29A.

FIG. 30A is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 30B is a sectional view taken along line X-X′ in FIG. 30A, and FIG. 30C is a sectional view taken along line Y-Y′ in FIG. 30A.

FIG. 31A is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 31B is a sectional view taken along line X-X′ in FIG. 31A, and FIG. 31C is a sectional view taken along line Y-Y′ in FIG. 31A.

FIG. 32A is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 32B is a sectional view taken along line X-X′ in FIG. 32A, and FIG. 32C is a sectional view taken along line Y-Y′ in FIG. 32A.

FIG. 33A is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 33B is a sectional view taken along line X-X′ in FIG. 33A, and FIG. 33C is a sectional view taken along line Y-Y′ in FIG. 33A.

FIG. 34A is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 34B is a sectional view taken along line X-X′ in FIG. 34A, and FIG. 34C is a sectional view taken along line Y-Y′ in FIG. 34A.

FIG. 35A is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 35B is a sectional view taken along line X-X′ in FIG. 35A, and FIG. 35C is a sectional view taken along line Y-Y′ in FIG. 35A.

FIG. 36A is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 36B is a sectional view taken along line X-X′ in FIG. 36A, and FIG. 36C is a sectional view taken along line Y-Y′ in FIG. 36A.

FIG. 37A is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 37B is a sectional view taken along line X-X′ in FIG. 37A, and FIG. 37C is a sectional view taken along line Y-Y′ in FIG. 37A.

FIG. 38A is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 38B is a sectional view taken along line X-X′ in FIG. 38A, and FIG. 38C is a sectional view taken along line Y-Y′ in FIG. 38A.

FIG. 39A is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 39B is a sectional view taken along line X-X′ in FIG. 39A, and FIG. 39C is a sectional view taken along line Y-Y′ in FIG. 39A.

FIG. 40A is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 40B is a sectional view taken along line X-X′ in FIG. 40A, and FIG. 40C is a sectional view taken along line Y-Y′ in FIG. 40A.

FIG. 41A is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 41B is a sectional view taken along line X-X′ in FIG. 41A, and FIG. 41C is a sectional view taken along line Y-Y′ in FIG. 41A.

FIG. 42A is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 42B is a sectional view taken along line X-X′ in FIG. 42A, and FIG. 42C is a sectional view taken along line Y-Y′ in FIG. 42A.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A manufacturing process for forming a SGT structure according to an embodiment of the present invention is described below with reference to FIGS. 2A-C to 42A-C.

First, a manufacturing method for forming a fin-shaped silicon layer on a silicon substrate, forming a first insulating film around the fin-shaped silicon layer, and forming a pillar-shaped silicon layer on the fin-shaped silicon layer is described. As shown in FIGS. 2A-C, a first resist 102 is formed for forming a fin-shaped silicon layer on a silicon substrate 101.

As shown in FIGS. 3A-C, the silicon substrate 101 is etched to form a fin-shaped silicon layer 103. Although, in this case, the fin-shaped silicon layer is formed using the resist as a mask, a hard mask such as an oxide film or a nitride film may be used.

As shown in FIGS. 4A-C, the first resist 102 is removed.

As shown in FIGS. 5A-C, a first insulating film 104 is deposited around the fin-shaped silicon layer 103. As the first insulating film, an oxide film formed by high-density plasma, or an oxide film formed by low-pressure chemical vapor deposition may be used.

As shown in FIGS. 6A-C, the first insulating film 104 is etched back to expose an upper portion of the fin-shaped silicon layer 103. The steps up to this step are the same as in the method for forming a fin-shaped silicon layer of Japanese Unexamined Patent Application Publication No. 2-188966.

As shown in FIGS. 7A-C, a second resist 105 is formed so as to be perpendicular to the fin-shaped silicon layer 103. A portion where the fin-shaped silicon layer 103 and the second resist 105 intersect at right angles becomes a pillar-shaped silicon layer. Since a linear resist can be used, the resist is unlikely to fall after patterning, thereby realizing a stable process.

As shown in FIGS. 8A-C, the fin-shaped silicon layer 103 is etched. A portion where the fin-shaped silicon layer 103 and the second resist 105 intersect at right angles becomes the pillar-shaped silicon layer 106. Therefore, the width of the pillar-shaped silicon layer 106 is equal to the width of the fin-shaped silicon layer. As a result, a structure is formed, in which the pillar-shaped silicon layer 106 is formed in an upper portion of the fin-shaped silicon layer 103, and the first insulating film 104 is formed around the fin-shaped silicon layer 103.

As shown in FIGS. 9A-C, the second resist 105 is removed.

Next, a description is given of a manufacturing method for forming diffusion layers by implanting impurities in an upper portion of the pillar-shaped silicon layer, an upper portion of the fin-shaped silicon layer, and a lower portion of the pillar-shaped silicon layer in order to use a gate-last process. As shown in FIGS. 10A-C, a second oxide film 107 is deposited, and a first nitride film 108 is formed. Since an upper portion of the pillar-shaped silicon layer is subsequently covered with a gate insulating film and a polysilicon gate electrode, a diffusion layer is formed in an upper portion of the pillar-shaped silicon layer before covering of the pillar-shaped silicon layer.

As shown in FIGS. 11A-C, the first nitride film 108 is etched to be left as a wide wall.

As shown in FIGS. 12A-C, impurities such as arsenic, phosphorus, or boron are implanted to form a diffusion layer 110 in an upper portion of the pillar-shaped silicon layer, and diffusion layers 109 and 111 in an upper portion of the fin-shaped silicon layer 103.

As shown in FIGS. 13A-C, the first nitride film 108 and the second oxide film 107 are removed.

As shown in FIGS. 14A-C, heat treatment is performed. The diffusion layers 109 and 111 in an upper portion of the fin-shaped silicon layer 103 are brought into contact with each other to form a diffusion layer 112. As described above, in order to use the gate-last process, the diffusion layers 110 and 112 are formed by impurity implantation in an upper portion of the pillar-shaped silicon layer and in an upper portion of the fin-shaped silicon layer and a lower portion of the pillar-shaped silicon layer.

Next, a description is given of a manufacturing method for forming a polysilicon gate electrode and a polysilicon gate wiring using polysilicon in order to use the gate-last process. In order to use the gate-last process, an interlayer insulating film is deposited, and then the polysilicon gate electrode and the polysilicon gate wiring are exposed by chemical mechanical polishing. Therefore, it is necessary to prevent an upper portion of the pillar-shaped silicon layer from being exposed by chemical mechanical polishing.

As shown in FIGS. 15A-C, a gate insulating film 113 is formed, and polysilicon 114 is deposited and then planarized. After planarization, the upper surface of the polysilicon is higher than the gate insulating film 113 disposed on the diffusion layer 110 in an upper portion of the pillar-shaped silicon layer 106. As a result, when in order to use the gate-last process, the polysilicon gate electrode and the polysilicon gate wiring are exposed by chemical mechanical polishing after the interlayer insulating film is deposited, the upper portion of the pillar-shaped silicon layer is not exposed by chemical mechanical polishing.

In addition, a second nitride film 115 is deposited. The second nitride film is one which inhibits the formation of silicide in upper portions of the polysilicon gate electrode and the polysilicon gate wiring when the silicide is formed in an upper portion of the fin-shaped silicon layer.

As shown in FIGS. 16A-C, a third resist 116 is formed for forming the polysilicon gate electrode and the polysilicon gate wiring. A portion corresponding to gate wiring is preferably perpendicular to the fin-shaped silicon layer 103. This is because a parasitic capacitance between the gate wiring and the substrate is decreased.

As shown in FIGS. 17A-C, the second nitride film 115 is etched.

As shown in FIGS. 18A-C, the polysilicon 114 is etched to form a polysilicon gate electrode 114 a and a polysilicon gate wiring 114 b.

As shown in FIGS. 19A-C, the gate insulating film 113 is etched.

As shown in FIGS. 20A-C, the third resist 116 is removed.

The manufacturing method for forming the polysilicon gate electrode and the polysilicon gate wiring using polysilicon in order to use the gate-last process is described above. After the polysilicon gate electrode 114 a and the polysilicon gate wiring 114 b are formed, the upper surface of polysilicon is higher than the gate insulating film 113 on the diffusion layer 110 in an upper portion of the pillar-shaped silicon layer 106.

Next, a manufacturing method for forming a silicide in an upper portion of the fin-shaped silicon layer is described. The silicide is not formed in upper portions of the polysilicon gate electrode 114 a and the polysilicon gate wiring 114 b and in the diffusion layer 110 in an upper portion of the pillar-shaped silicon layer 106. When the silicide is formed in the diffusion layer 110 in an upper portion of the pillar-shaped silicon layer 106, the manufacturing process is enlarged.

As shown in FIGS. 21A-C, a third nitride film 117 is deposited.

As shown in FIGS. 22A-C, the third nitride film 117 is etched to be left as a side wall.

As shown in FIGS. 23A-C, a metal such as nickel or cobalt is deposited to form silicide 118 in an upper portion of the diffusion layer 112 formed in an upper portion of the fin-shaped silicon layer 103. At this time, the polysilicon gate electrode 114 a and the polysilicon gate wiring 114 b are covered with the third nitride film 117 and the second nitride film 115, and the diffusion layer 110 in an upper portion of the pillar-shaped silicon layer 106 is covered with the gate insulating film 113, the polysilicon gate electrode 114 a, and the polysilicon gate wiring 114 b, and thus silicide is not formed in the polysilicon gate electrode 114 a, the polysilicon gate wiring 114 b, and the diffusion layer 110.

The manufacturing method for forming a silicide in an upper portion of the fin-shaped silicon layer is described above.

Next, a gate-last manufacturing method is described, in which the polysilicon gate electrode and the polysilicon wiring are exposed by chemical mechanical polishing after an interlayer insulting film is deposited, the polysilicon gate electrode and the polysilicon wiring are etched, and then a metal is deposited.

As shown in FIGS. 24A-C, a fourth nitride film 140 is deposited for protecting the silicide 118.

As shown in FIGS. 25A-C, an interlayer insulating film 119 is deposited and then planarized by chemical mechanical polishing.

As shown in FIGS. 26A-C, the polysilicon gate electrode 114 a and the polysilicon gate wiring 114 b are exposed by chemical mechanical polishing.

As shown in FIGS. 27A-C, the polysilicon gate electrode 114 a and the polysilicon gate wiring 114 b are etched. Wet etching is preferred.

As shown in FIGS. 28A-C, a metal 120 is deposited and then planarized to fill, with the metal 120, a portion from which the polysilicon gate electrode 114 a and the polysilicon gate wiring 114 b have been removed. Atomic layer deposition is preferably used.

As shown in FIGS. 29A-C, the metal 120 is etched to expose the gate insulating film 113 formed on the diffusion layer 110 in an upper portion of the pillar-shaped silicon layer 106. Consequently, a metal gate electrode 120 a and a metal gate wiring 120 b are formed. The gate-last manufacturing method is described above, in which after the interlayer insulating film is deposited, the polysilicon gate is exposed by chemical mechanical polishing, the polysilicon gate is etched, and then a metal is deposited.

Next, a manufacturing method for forming a contact is described. Since a silicide is not formed in the diffusion layer 110 in an upper portion of the pillar-shaped silicon layer 106, a contact is brought into direct contact with the diffusion layer 110 in an upper portion of the pillar-shaped silicon layer 106. As shown in FIG. 30, an interlayer insulating film 121 is deposited and then planarized.

As shown in FIGS. 31A-C, a fourth resist 122 is formed for forming a contact hole on the pillar-shaped silicon layer 106.

As shown in FIGS. 32A-C, the interlayer insulating film 121 is etched to form a contact hole 123.

As shown in FIGS. 33A-C, the fourth resist 122 is removed.

As shown in FIGS. 34A-C, a fifth resist 124 is formed for forming contact holes on the metal gate wiring 120 b and on the fin-shaped silicon layer 103.

As shown in FIGS. 35A-C, the interlayer insulating films 121 and 119 are etched to form contact holes 125 and 126.

As shown in FIGS. 36A-C, the fifth resist 124 is removed.

As shown in FIGS. 37A-C, the nitride film 140 and the gate insulating film 113 is etched to expose the silicide 118 and the diffusion layer 110.

As shown in FIGS. 38A-C, a metal is deposited to form contacts 143, 127, and 128. The manufacturing method for forming contacts is described above. Since a silicide is not formed in the diffusion layer 110 in an upper portion of the pillar-shaped silicon layer 106, the contact 127 is brought into direct contact with the diffusion layer 110 in an upper portion of the pillar-shaped silicon layer 106.

Next, a manufacturing method for forming a metal wiring layer is described.

As shown in FIGS. 39A-C, a metal 129 is deposited.

As shown in FIGS. 40A-C, sixth resists 130, 131, and 132 are formed for forming the metal wiring.

As shown in FIGS. 41A-C, the metal 129 is etched to metal wirings 133, 134, and 135.

As shown in FIGS. 42A-C, the sixth resists 130, 131, and 132 are removed.

The manufacturing method for forming metal wiring layers is described above.

The result of the above-described manufacturing method is shown in FIGS. 1A-C.

The resulting structure includes: the fin-shaped silicon layer 103 formed on the substrate 101; the first insulating film 104 formed around the fin-shaped silicon layer 103; the pillar-shaped silicon layer 106 formed on the fin-shaped silicon layer 103, the width of the pillar-shaped silicon layer 106 being equal to the width of the fin-shaped silicon layer 103; the diffusion layer 112 formed in an upper portion of the fin-shaped silicon layer 103 and a lower portion of the pillar-shaped silicon layer 106; the diffusion layer 110 formed in an upper portion of the pillar-shaped silicon layer 106; the silicide 118 formed in an upper portion of the diffusion layer 112 in an upper portion of the fin-shaped silicon layer 103; the gate insulating film 113 formed around the pillar-shaped silicon layer 106; the metal gate electrode 120 a formed around the gate insulating film; the metal gate wiring 120 b connected to the metal gate electrode 120 a and extending in a direction perpendicular to the fin-shaped silicon layer 103; and the contact 127 formed on the diffusion layer 110, the diffusion layer 110 and the contact 127 being in direct contact with each other.

As described above, it is possible to decrease a parasitic capacitance between a gate wiring and a substrate and provide a SGT manufacturing method using a gate-last process and a resulting SGT structure. 

1. A semiconductor device comprising: a fin-shaped silicon layer on a surface of a silicon substrate, the fin-shaped silicon layer having a longitudinal axis extending in a first direction parallel to the surface; a first insulating film around the fin-shaped silicon layer; a pillar-shaped silicon layer on the fin-shaped silicon layer, a pillar diameter of the bottom of the pillar-shaped silicon layer being equal to a fin width of the top of the fin-shaped silicon layer, the pillar diameter and the fin width parallel to the surface of the silicon substrate; a gate insulating film around the pillar-shaped silicon layer; a metal gate electrode around the gate insulating film; and a metal gate wiring connected to the metal gate electrode, the metal gate wiring having a longitudinal axis extending in a second direction parallel to the surface and perpendicular to the first direction of the longitudinal axis of the fin-shaped silicon layer.
 2. The semiconductor device of claim 1, wherein the gate insulating film separates the metal gate electrode from the first diffusion layer in the upper portion of the fin-shaped silicon layer.
 3. The semiconductor device of claim 2, wherein the gate insulating film contacts the first insulating film and separates the metal gate wiring from the first insulating film.
 4. The semiconductor device of claim 1, wherein an upper surface of the first insulating film is on a same lateral plane with an upper surface of the first diffusion layer in the upper portion of the fin-shaped silicon layer, the lateral plane parallel to the surface. 